Among parallel computers, there is a device including a plurality of computers called compute nodes. In such a parallel computer including a plurality of compute nodes, data is transferred in some cases between compute nodes through direct memory access (DMA). In such cases, each compute node includes a DMA controller.
The DMA controller in a compute node, which functions as the data receiver, receives data transferred as packets via an input/output (I/O) controller from a compute node, which functions as the data transmitter. Next, the DMA controller stores the received data in a receive buffer. The DMA controller then writes the payload portion of the data, which has been stored in the receive buffer by DMA, to a memory.
In order to transfer payloads with long message lengths at high throughput by DMA, a receive buffer for storing a large amount of payloads is to be implemented, which leads to an increase in resources provided in an information processing apparatus. Such an increase in resources leads to suppressing space saving and an increase in manufacturing costs of the information processing apparatus.
Accordingly, to suppress an increase in resources while improving throughput, a high-density buffer, such as static random access memory (SRAM), is often used as a receive buffer of a DMA controller. For the purpose of improving the throughput of data transfer by DMA, the DMA controller uses a high-density receive buffer, such as SRAM, to store a large amount of packets. Storing a large amount of packets in a receive buffer enables the DMA controller to reduce waiting for transmission of packets at the transmitter end, and successively writing data retained in the receive buffer to a memory improves the throughput of data transfer. However, typically, access to SRAM has a long latency as compared with access to a usual receive buffer of flip-flops and the like.
As a technique for effectively making use of a receive buffer in data transfer by DMA as mentioned, there is an existing technique that provides different receive buffers for variable-length packets and for fixed-length packets. There is another existing technique that provides a plurality of per-destination receive buffers and in which when transfer conditions are satisfied in a receive buffer, data in the receive buffer is transferred to a memory by DMA.
Related art techniques are disclosed, for example, in Japanese Laid-open Patent Publication No. 11-146019 and Japanese Laid-open Patent Publication No. 2000-92066.